This document specifies the layout and routing strategy for the 64-coil set integrated PCB stator.
Adherence to the stackup defined in PCB Stator Design Parameters is mandatory:
| Layer | Function | Routing Strategy |
|---|---|---|
| Layer 1 | Sensing Coil | Minimal trace width for signal integrity, differential pair routing. |
| Layer 2 | GND Plane | Solid copper pour, isolated from Power layers. |
| Layer 3 | Power A | High-current traces, wide geometry to minimize resistance. |
| Layer 4 | Power B | High-current traces, wide geometry to minimize resistance. |
| Layer 5 | Power C | High-current traces, wide geometry to minimize resistance. |
| Layer 6 | Aluminum Backing | Integrated thermal interface. |
Status: Draft pending CAD implementation.